Ferroelectric random-access memories (F-RAM) typically include a grid or an array of storage elements or cells, each including at least one ferroelectric capacitor and one or more associated transistors to select the cell and control reading or writing thereto.
When an external electric field is applied across a ferroelectric material of a ferroelectric capacitor in the cell, dipoles in the material align with the field direction. After the electric field is removed, the dipoles retain their polarization state. Data is stored in the cells as one of two possible electric polarizations in each data storage cell. For example, in a one transistor-one capacitor (1T1C) cell, a “1” may be encoded using a negative remnant polarization, and a “0” is encoded using a positive remnant polarization.
FIG. 1 illustrates a cross-sectional view of a portion of a F-RAM cell 100 fabricated according to a conventional method. Referring to FIG. 1, the ferroelectric capacitor 102 in an F-RAM cell typically includes a ferroelectric material 104 between an upper electrode 106 and a lower electrode 108. Transistors 110 in the cell 100 are typically metal-oxide-semiconductor (MOS) transistors fabricated on a substrate 112 using a standard or baseline complimentary-metal-oxide-semiconductor (CMOS) process flows, involving the formation and patterning of conducting, semiconducting, dielectric and materials. The composition of these materials, as well as the composition and concentration of processing reagents, and temperature used in such a CMOS process flow are stringently controlled for each operation to ensure the resultant MOS transistors will function properly. Thus, in conventional methods of fabricating F-RAM the ferroelectric capacitor 102 is fabricated in a separate F-RAM layer 114 overlying a CMOS layer 116 in which the MOS transistors 110 are fabricated and connected thereto by one or more contacts 118 extending to a diffusion region 120 of the MOS transistor in the substrate 112 and/or by a separate wiring layer 122 fabricated in yet another dielectric layer 124 overlying the F-RAM layer 112 and connected to the MOS transistors and ferroelectric capacitor through additional contacts 126.
Materials and processes typically used to fabricate the CMOS transistors 110, contacts 118 and wiring layer 122 are incompatible with ferroelectric capacitor process flow, and can detrimentally impact their performance. In particular, when fabricating the ferroelectric capacitor 102 over a contact 118 in the CMOS layer 116 processes used to fabricate the ferroelectric capacitor can oxidize a metal used in the contact. Thus, ferroelectric capacitors 102 formed over such contacts 118 typically must include an oxygen barrier 128 between the contact and bottom electrode.
It will be understood by those skilled in the art that the above described conventional method of fabricating F-RAM undesirably increases an aspect ratio of the ferroelectric capacitors 102, as well as the overall size or height of the F-RAM cell 100, and require several extra mask and processing steps, all of which increase fabrication time, costs, and defect density lowering a yield of working memories.